In recent years there has been a much increased demand for devices with wireless functionality, for example WI-FI, Bluetooth and GPS. In most wireless communication systems, information is transmitted at a much higher frequency than the signal bandwidth. Reducing the wavelength information is transmitted at often increases the effectiveness of the communication. For example, in wireless communications devices decreasing the wavelength of the transmitted signal allows the antenna of the receiver device to be made smaller. The frequency at which information is transmitted is known as the carrier frequency. A phase-locked loop (PLL) is commonly used to generate this carrier frequency. An example of a typical PLL is shown in FIG. 1. A reference signal Sref with frequency Fref and a second signal S0 are input into a phase detector module 101. The phase difference is output as a signal e(t) which in turn is input into a filter 102. The output signal from the filter v(t) is input into a voltage-controlled oscillator (VCO) 103 which, in response to the input signal, outputs a signal S0. The signal S0 is then fed back into the phase detector along with the reference signal Sref. The PLL acts as a feedback loop whereby the measured phase difference between the generated signal and a reference signal is used to drive the oscillator that outputs the generated signal. If the phase detector measures a phase difference between the two input signals, it outputs an error signal in dependence on this difference. The error signal is input into the loop filter and the signal output from the loop filter is input into the VCO. The VCO will then generate a signal with a frequency that is closer to the reference frequency which will reduce the phase difference.
When the phase difference between the signal generated by the VCO and the reference signal is small and measured errors cause the VCO to bring the frequency of its output signal back towards the reference signal, the generated signal is said to be locked-on to the reference signal. In this mode if the frequency of the reference signal changes, the measured error signal can cause the VCO to generate a signal with a frequency that tracks that of the reference signal. When this happens the PLL is said to be in “tracking mode”. When the PLL is in tracking mode it is also locked on to the reference signal. If the PLL is in “acquisition mode” the PLL is not locked on to the reference signal. This could be because lock-in has yet to be achieved or because the VCO has received an instantaneous frequency kick. Frequency kicks can be caused by, for example, the dynamic variation of the output impedance of the VCO; from supply pulling or from substrate pushing. Substrate pushing is the effect of signals from one node of an integrated circuit coupling to another node via the substrate of the circuit. Supply pulling describes the effect of the output frequency of the VCO changing in response to a change in load of the output signal In “acquisition mode” the measured phase error between the output signal from the VCO and the reference signal is relatively large. The time taken for a PLL to achieve lock-in from an unlocked state is called the lock-in time. If the PLL is locked on to the reference signal and the controlled oscillator receives an instantaneous frequency kick, the subsequent behaviour of the PLL is called the step response. An important factor in the step response is the time taken for the PLL to once again lock-on to the reference signal.
The phase detector, filter and VCO are each associated with a “gain”. The gain helps to define the relationship between the input signal and output signal of a component of the PLL. The relationship between the input and output signals of the phase detector, filter and VCO may be given by the following respective equations:e(t)=Kpdf1(Δφ)v(t)=Kfilterf2(Δφ)S1=KVCOf3(v(t))where kpa, Kfilter and KVCO are the gains of the phase detector, filter and VCO respectively, Δφ is the measured phase difference and f1, f2 and f3 are functions. In phase detectors with a linear response, f1(Δφ)=Δφ.
Recent developments have focussed on digital PLLs due to their improved scalability as circuit components shrink in size. An example of a digital PLL is shown in FIG. 2. The circuit operates in the same manner as the circuit depicted in FIG. 1, with a Time-to-Digital Converter (TDC) 201 performing the function of phase comparison between the reference signal and the generated signal. The loop filter and controlled oscillator of FIG. 1 have also been replaced by their digital equivalents; a digital loop filter (DLF) 202 and a digitally controlled oscillator (DCO) 203 respectively. Each of the components will have a gain associated with them. A TDC measures the time difference between two signals. In a typical application of a TDC in a PLL, one of the signals is delayed multiple times relative to the reference signal. After each time the signal has been delayed it is determined whether the rising edge of that signal is ahead or behind of the rising edge of the reference signal. If the signal is ahead of the reference signal, a digital counter is incremented, whereas if the signal is behind the reference signal the counter is not incremented. This process is illustrated in FIGS. 3a and 3b. FIG. 3a shows a reference signal Sref and a generated signal S0. The time difference between the rising edges of the signals is given by ΔT0. The rising edge of signal S0 passes a fixed reference point X in advance of the rising edge of signal Sref, and so the digital counter is incremented. The signal S0 is then delayed relative to the reference signal by an amount ΔT1, to produce signal S1. The rising edge of signal S1 still passes the point X in advance of the rising edge of the reference signal, and so the digital counter is again incremented. Signal S1 is then delayed relative to the reference signal by an amount ΔT2, to produce signal S2 which causes the digital counter to be incremented once again. Delaying signal S2 by an amount ΔT3 does not cause the counter to be further incremented because the rising edge of the resulting signal S3 passes the point X after the rising edge of the reference signal. FIG. 3b is an illustration of the digital output of the TDC for a time error ΔT0 between a reference signal and generated signal. Because of the simple relationship between the time delay between two signals and the corresponding phase difference, it is possible to determine the digital output of the TDC for a particular phase difference between two signals if the temporal difference is known. An example of such an output is shown in FIG. 3b. 
It can be seen with reference to FIG. 3a that delaying the signal relative to the reference signal by a quantized amount introduces an error, ΔTE. It is not possible for the TDC to determine where within the time period ΔT3 the rising edges of the reference signal and the generated signal overlap, meaning it is not possible to fully determine the value of ΔT0. Mathematically we have the relationship:ΔT0=ΔT1+ΔT2+ΔT3±ΔTE 
In order to improve the temporal resolution it is therefore necessary to decrease the size of the delay periods ΔTn. However each delayed signal is generated by a digital delay gate, and so in order to increase the resolution whilst maintaining the range of initial time differences that the TDC is able to detect, it is necessary to increase the number of delay gates. This would lead to an increase in occupied chip area and a more power-hungry circuit. A further potential problem with the TDC is that if the delay periods ΔTn are not constant then the linearity of the relationship between the output of the TDC and the measured time difference is reduced.
Alternatively a digital PLL may implement a Binary Phase Detector (BPD) instead of a TDC. Unlike a TDC, a BPD can generally only determine the polarity of the phase difference between a generated signal and a reference signal; that is, whether the rising edge of the generated signal passes before or after the rising edge of the reference signal. The magnitude of the difference remains unknown. FIG. 4 shows the output of a BPD as a function of phase difference. Because the BPD output is a non-linear function of the phase difference, the output signal of the controlled oscillator is oscillatory when the PLL is in a phase tracking mode. The non-linear behaviour also means that PLLs with BPDs are not able to be analysed using linear analysis techniques, which can make their design more difficult to optimise. Despite these potential drawbacks, BPDs are often used in digital PLLs because they are capable of achieving a very high temporal resolution in the range of 0.2 ps. It is therefore easier to implement a PLL with a high temporal resolution using a BPD than it is with a TDC. However, BPDs typically limit the capture range of the PLL to approximately 10% of the controlled oscillator's free-running frequency. The capture range is defined as the maximum difference in frequency between the two signals input into phase detector that will still result in the PLL being able to lock onto the reference frequency. Furthermore when the PLL is not locked and the phase difference between the generated signal and the reference signal is relatively large, the gain of the BPD is significantly reduced. This results in the step response of the loop being reduced.
It is desirable to produce a PLL which has a large capture range and high temporal resolution without the burden of significantly increasing the circuit size and complexity. There is thus a need for improved phase detection for use in PLLs.